The present invention relates to a consecutive identical digit supression system, in particular relates to such a system for the use in a digital transmission system in an optical fiber communications system.
In a digital transmission system, a consecutive identical digit (consecutive identical marks, or spaces) are not desirable, because (1) a clock timing for regenerating a symbol is not kept correctly in a long consecutive identical digit condition, and (2) the level of a signal fluctuates depending upon the information to be transmitted. Thus, the consecutive identical digit deteriorates the transmission quality and generates undesirable transmission errors.
Accordingly, a pair of code conversion circuits (encoder an decoder) have been utilized in a digital transmission system to prevent too many consecutive identical digits.
FIG. 1 is the typical block diagram of a digital transmission system, in which the reference numeral 210 is a data input terminal, 110 is a transmission speed conversion circuit, 120 is a frame assembler, 130 is a scrambler, 140 is a code converter or a consecutive identical digit suppression circuit, 150 is a transmission line, 160 is a code disassembler for disassembling the code for reproducing the signal which is assembled by the code converter 140, 170 is a frame synchronization circuit, 180 is a disscrambler which reproduces the signal which is scrambled by the scrambler 130, 190 is a bit rate conversion circuit for reproducing the signal converted by the circuit 110, and 200 is an output terminal for providing output data.
Tne scrambler 130 and the disscrambler 180 provide the balanced code in which the possibility of the code "1" and the possibility of the code "0" become similar during a long duration. The scrambler and the disscrambler are described in the article "PCM Jitter Suppression by Scrambling" by H. Kasai et al in IEEE Transactions on communications, vol. COM-22, No. 8, August 1974, pages 1114-1122.
However, the scrambler and/or the disscrambler can provide only the possibility that the consecutive identical digit is less than the predetermined value. Therefore, the length of the consecutive identical digit of the output of the scrambler depends upon the input data, and the scrambler can not guarantee that the maximum length of the consecutive identical digit is less than the desired value. Thus, a code converter 140 is introduced in order to guarantee that the length of the consecutive identical digit does not exceed a predetermined value, and provide a BSI (Bit Sequence Independence) signal.
One of prior code converters 140 is a block conversion system, in which a block with m number of bits is converted to a block with n number of bits. For instance, in 3B4B code in which a block with 3 bits is converted to a block 4 bits, and a typical conversion algorithm for that conversion determines the sign of the fourth bit so that the number of "1" digits in each block (four bits) is 2 for input codes 001 through 110, an input code "000" is coded to "0100" and "1011" alternately, and an input code "111" is coded to "0010" and "1101" alternately. Therefore, the following relations are satisfied between an input 3 bit code and an output 4 bit code.
______________________________________ Input Output ______________________________________ 000 0100 or 1011 001 0011 010 0101 011 0110 100 1001 101 1010 110 1100 111 0010 or 1101 ______________________________________
However, that mBnB code has the disadvantage that the number of transmission error is increased through an encoding and decoding. For instance, it is assumed that an original code is "001" in the above table. The original code is encoded to "0011", which is transmitted into a transmission line. Then, it is assumed that the code "0011" is changed to "0010" due to a transmission error by a noise (the fourth bit is in error). The receive side decodes the code "0010" to the code "111" according to the above table. As a result, the original code "001" is reproduced as "111". It should be appreciated in the above procedure that a single transmission error causes two bits of error in a receive side, and the number of errors in a transmission line is increased through an encoding and decoding procedure. Of course, that increase of errors is not desirable.
Another block conversion system is the CMI (Coded Mark Inversion), which is described in the U.S. Pat. No. 4,189,621. In the CMI system, when the input data is "1", the output data is "11" or "00", which appears alternately, and when the input data is "0", the output data is "10". Thus, according to the CMI system, the length of the consecutive identical digit (consecutive identical "1" or "0") is 3.
However, the CMI system has the disadvantage that the pulse repetition frequency or the transmission speed of the encoded signal is twice as high as that of the input signal, since each input bit generates two output bits.
Other block conversion systems are the DMI (Differential Mode Inversion) and the Dipulse system. In the DMI system, a mode is switched by every input data "1", and in the first mode, the input data "1" is converted to "11" and the input data "0" is converted to "01", while in the second mode, the input data "1" is converted to "00" and the input data "0" is converted to "10". In the Dipulse system, each input data "1" is converted to "10" and each input data "0" is converted to "01". However, both the DMI system, and the Dipulse system have the disadvantage that the output frequency or the transmission speed is much higher than that of the input signal, since a number of pulses for each of the data is increased through the conversion. As those systems raise the transmission speed considerably, those systems can both be used in a high speed digital transmission system which is higher than 100 Mbits/second.
Another prior code converter system is a bit insertion code system, in which mBlP (m Binary with l Parity) and PMSI (Periodic Mark Space Insertion) are typical ones.
In the mBlP system, an odd parity bit P(o) is inserted for each m bits of input data (see FIG. 2). In the mBlP system, the maximum number of the consecutive identical digit is 2m, and that length 2m is not short enough for high speed data transmission.
Another prior system, PMSI, inserts "1" and "0" alternately periodically for every m bits of input data (see FIG. 3). In the PMSI system, the maximum number of the consecutive identical digit is 2m+1, which is also not short enough for high speed data transmission. Further, in the PMSI system, a line spectrum is generated in a signal spectrum since a data "1" and "0" is inserted periodically, and that line spectrum would cause a jitter and deteriorates the margin for interference.
As described above, a prior consecutive identical digit suppression system is not suitable for a high speed latest digital transmission system, in which the transmission bit rate is higher then 100 Mbits/second, and the desirable maximum number of the consecutive identical digit is less than 12.
Some of the desirable natures of a consecutive identical digit suppression system are:
(1) the maximum number of the consecutive identical digit is short, and is preferably less than 12.
(2) the output frequency or the transmission speed is not so high as compared with that of the input signal.
(3) The high bit rate conversion for higher than 100 Mbits/second is possible. For the high bit rate conversion, a conversion circuit must be simple.
(4) An error in a transmission line is not increased through encoding the decoding procedure.